Pipelined Cyclic Redundancy Check for High Bandwith Interfaces
AssigneeInternational Business Machines Corporation
InventorsScott Douglas Clark, Dorothy Marie Thelen
Life of this patent
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Abstract
Techniques for validating the integrity of a data communications link are provided. By executing error correction/detection calculations, such as CRC calculations, in a pipelined manner, logic may be distributed over multiple machine cycles. As a result, delay involved in the logic for each cycle may be reduced, allowing calculations in systems with higher clock frequencies
Claims20
A method of calculating an error detection code in a pipelined manner, comprising:
- generating an intermediate value by performing a first portion of an error detection code algorithm, based on a multi-bit data structure, in a first pipeline stage in a first clock cycle;
- and
- generating a final value for the error detection code by performing a second portion of the error detection code algorithm, based on the intermediate value, in a second pipeline stage in a second clock cycle.
A pipelined circuit for generating a checksum for a multi-bit data structure, comprising:
- a first pipeline stage for generating an intermediate value by performing a first portion of an error detection code algorithm, based on the multi-bit data structure, in a first clock cycle;
- and
- at least a second pipeline stage for generating a final value of the checksum by performing a second portion of the error detection code algorithm, based at least on the intermediate value, in a second clock cycle.
An integrated circuit device, comprising:
- a communications link to connect with external devices;
- at least one processor core;
- input/output (I/O) logic for transferring data in packets between the processor core and the communications link;
- and
- checksum logic configured to calculate checksums to be appended to data packets transmitted from the device via the communications link and to calculate checksums to validate data received via the communications link, the checksum logic including,
- a first pipeline stage for generating an intermediate value by performing a first portion of an error detection code algorithm, based on the multi-bit data structure, in a first clock cycle, and
- at least a second pipeline stage for generating a final value of the checksum by performing a second portion of the error detection code algorithm, based at least on the intermediate value, in a second clock cycle.
Dependencies are inferred from the claim text.