Linked Random Access Memory (RAM) Interleaved Pattern Persistence Strategy

A method of detecting random access memory (RAM) failure for data with a plurality of addresses, the method comprising the steps of:

• generating a plurality of sets of RAM test patterns, each RAM test pattern set comprising two complementary RAM test patterns;
• grouping the plurality of data addresses into sets, each data address set comprising two different data addresses;
• assigning each RAM test pattern set to one or more corresponding data address sets;
• and
• implementing each RAM test pattern set on its corresponding one or more data address sets.

An apparatus for detecting random access memory (RAM) failure for data with a plurality of addresses, the apparatus comprising:

• (a) means for generating a plurality of RAM test patterns in a predetermined order;
• (b) means for implementing a RAM test pattern on each data address in an initial testing pass, based on the predetermined order of the RAM test patterns;
• (c) means for rotating the RAM test patterns sequentially to prepare for a new testing pass;
• and
• (d) means for implementing the RAM test patterns on different data addresses in the new testing pass.