Parallel bit test apparatus and parallel bit test method capable of reducing test time

A parallel bit test (PBT) method which simultaneously tests memory chips stacked in a multi-chip package (MCP), the memory chips sharing a set of data signal lines, the PBT method comprising:

• receiving a command to perform a PBT on the memory chips;
• outputting representative data signals that represent comparisons between groups of test data signals provided to the memory chips and corresponding groups of data signals output therefrom, respectively;
• selecting non-overlapping subsets of the one or more of the data signal lines amongst the shared set of data signal lines, the non-overlapping subsets corresponding to the memory chips, respectively;
• and
• outputting the representative data signals via the non-overlapping subsets of data signal lines, respectively.

A multi-chip package (MCP), comprising:

• memory chips that share a plurality of data signal lines;
• and
• a plurality of parallel bit test (PBT) apparatuses at least associated with the memory chips, respectively;
• each PBT apparatus including:
• a comparing unit to output a representative data signal that is representative of a comparison between test data signals provided to an associated one of the memory chips and corresponding data signals output therefrom, respectively;
• and
• a coding unit to output the representative data signal using a first subset of the shared set of data signal lines, the first subset not overlapping other subsets used by coding units corresponding to the other ones of the memory chips, respectively, the coding unit selecting one or more of the data signal lines amongst the shared set of data signal lines for inclusion in the first subset according to a first test mode register set (MRS) signal.