Soft error handling in microprocessors

A method for handling soft error in a microprocessor system, comprising:

• detecting a register file state soft error with a parity or ECC checking,
• indicating a register having soft error to an instruction unit,
• flushing microprocessor pipelines by removing the instruction having experienced the error as well as all subsequent instructions from issue queues and execution pipelines,
• identifying locations from which to recover a good architectural state based on execution resources used for processing;
• and
• recovering said good architectural state from duplicate execution resources used for processing, wherein recovery logic that is located in an instruction fetch, decode or sequencing unit is initiated, a register to register move iop is generated indicating the failing register as source and target, the iop is associated with a cluster steering bit to cause execution in the pipeline that did not generate the error condition, and a register copy instruction is executed, reading the good state from a register file, using its associated execution pipeline executing register copy, and write updating both a first and second register file copy, thereby ensuring that both register file states have the correct value.