Methods and Apparatus for Calibrating Heterogeneous Memory Interfaces

An apparatus for interfacing a processor and a memory of a computer system, comprising:

• a translation chip adapted to couple to the processor via a first link and to the memory via a second link;
• the translation chip having:
• first logic adapted to calibrate the first link;
• and
• second logic adapted to calibrate the second link while the first logic calibrates the first link.

A system for interfacing a processor and a memory of a computer system, comprising:

• a memory;
• a processor adapted to issue a functional command to the memory;
• a translation chip;
• a first link adapted to couple the processor to the translation chip;
• and
• a second link adapted to couple the translation chip to the memory;
• wherein the translation chip is adapted to:
• calibrate the first link;
• and
• while calibrating the first link, calibrate the second link.