US 2008/0168293 A1 · METHOD AND APPARATUS FOR REDUCING LATENCY ASSOCIATED WITH READ OPERATIONS IN A MEMORY SYSTEM

Abstract

Methods and system for reducing latency associated with a read operation in a processor memory system are provided. In one implementation, the method includes receiving an early indicator corresponding to read data from a memory, delaying the early indicator in accordance with a pre-determined delay such that the early read indicator is passed to a bus in advance of the read data; and dynamically adjusting the pre-determined delay using an adjustment delay circuit, the pre-determined delay being adjusted responsive to a change in operational speed of the bus or change in operational speed of a processor coupled to the bus.

Claims19

Dependent claims

A processor memory system comprising:

a processor;
and
a memory controller in communication with the processor through a bus, the memory controller including,
a delay circuit to receive an early read indicator corresponding to read data from a memory, the delay circuit to delay the early read indicator in accordance with a pre-determined delay such that the early read indicator is passed to the bus in advance of the read data;
and
a delay adjustment circuit to dynamically adjust the pre-determined delay associated with the delay circuit responsive to a change in operational speed of the processor or the bus.

3 more elements

Dependencies are inferred from the claim text.

Method and apparatus for reducing latency associated with read operations in a memory system

Life of this patent

Method and apparatus for reducing latency associated with read operations in a memory system

Life of this patent

Abstract

Claims19