Method and Apparatus for Power Throttling a Processor in an Information Handling System
AssigneeIBM Corporation
InventorsRobert Walter Berry, Charles Ray Johns, Christopher J. Kuruts
Life of this patent
Estimating the term…
Abstract
A power system couples to a multi-core processor to provide power to the processor. The power system throttles at least one of the cores of the processor when the power that the processor consumes from the power system exceeds a predetermined threshold power. The power system may reduce the rate of instruction issue by a particular core or clock gate a particular core to provide power throttling. The power system dynamically responds to variance of the actual output voltage that processor circuitry receives from the power system in comparison to an expected output voltage over time and corrects for such variance.
Claims20
A method of providing power to a processor that includes processor circuitry on a semiconductor substrate, the method comprising:
- supplying, by a power system, power to the processor wherein the processor circuitry includes a plurality of cores;
- throttling, by the power system, at least one core of the processor if power that the processor consumes from the power system exceeds a predetermined threshold power thus placing the processor in a power throttled mode;
- determining, by the power system, an actual output voltage that the processor circuitry in the processor receives from the power system;
- and
- varying, by the power system, the actual output voltage dynamically over time in response to a detected difference between the actual output voltage and an expected output voltage of the power system.
A processor system comprising:
- a processor that includes processor circuitry having a plurality of cores situated on a semiconductor substrate;
- a power system, coupled to the processor, that supplies power to the processor, the power system including:
- a power controller that throttles at least one core of the processor if the processor consumes more than a predetermined threshold power, thus placing the processor in a power throttled mode;
- a sensor, coupled to the processor circuitry and the power controller, that senses an actual output voltage that the processor circuitry receives from the power system;
- and
- a voltage regulator, coupled to the power controller and the processor, that varies the actual output voltage dynamically over time under the control of the power controller in response to a difference the power controller detects between the actual output voltage and an expected output voltage of the voltage regulator.
An information handling system (IHS) comprising:
- a processor that includes processor circuitry having a plurality of cores situated on a semiconductor substrate;
- a memory coupled to the processor;
- and
- a power system, coupled to the processor, that supplies power to the processor, the power system including:
- a power controller that throttles at least one core of the processor if the processor consumes more than a predetermined threshold power, thus placing the processor in a power throttled mode,
- a sensor, coupled to the processor circuitry and the power controller, that senses an actual output voltage that the processor circuitry receives from the power system;
- and
- a voltage regulator, coupled to the power controller and the processor, that varies the actual output voltage dynamically over time under the control of the power controller in response to a difference the power controller detects between the actual output voltage and an expected output voltage of the voltage regulator.
Dependencies are inferred from the claim text.