Methods and Systems for Power Management in a Data Processing System

A data processing system comprising:

• a processing unit;
• at least one bus coupled to the processing unit;
• at least one subsystem coupled to the at least one bus;
• a power controller coupled to the processing unit and to the at least one subsystem, the power controller being configured to reduce power consumed by the at least one subsystem in response to a first state of an instruction queue in memory for the at least one subsystem, the instruction queue being accessible to a software driver for the at least one subsystem which communicates the status of the first state to the processing unit which in response reduces power, through the power controller, to the at least one subsystem, and wherein the first state represents an instruction queue having either no instructions or only instructions for future events or actions.

A machine implemented method comprising:

• determining a state of an instruction queue of a graphics processing unit;
• turning off power to the graphics processing unit in response to determining that the instruction queue of the graphics processing unit (GPU) has either no instructions or instructions for only future events or actions, wherein the GPU has its power turned off while an image, generated by the graphics processing unit, is being displayed;
• determining a state of an instruction queue of a general purpose processing unit;
• turning off power to the general purpose processing unit in response to determining that the instruction queue of the general purpose processing unit has either no instructions or instructions for only future events or actions.

A machine readable medium containing executable program instructions which cause a data processing system to perform a method comprising:

• determining a state of an instruction queue of a graphics processing unit;
• turning off power to the graphics processing unit in response to determining that the instruction queue of the graphics processing unit (GPU) has either no instructions or instructions for only future events or actions, wherein the GPU has its power turned off while an image, generated by the graphics processing unit, is being displayed;
• determining a state of an instruction queue of a general purpose processing unit;
• turning off power to the general purpose processing unit in response to determining that the instruction queue of the general purpose processing unit has either no instructions or instructions for only future events or actions.

A data processing system comprising:

• means for determining a state of an instructions queue of a graphics processing unit;
• means for turning off power to the graphics processing unit in response to determining that the instruction queue of the graphics processing unit (GPU) has either no instructions or instructions for only future events or actions, wherein the GPU has its power turned off while an image, generated by the graphics processing unit, is being displayed;
• means for determining a state of an instruction queue of a general purpose processing unit;
• means for turning off power to the general purpose processing unit in response to determining that the instruction queue of the general purpose processing unit has either no instructions or instructions for only future events or actions.

A data processing system comprising:

• a processing unit;
• at least one bus coupled to the processing unit;
• at least one subsystem coupled to the at least one bus;
• a memory coupled to the at least one bus;
• a power controller coupled to the processing unit, wherein the memory is configured to store data representing a future action for at least one of the subsystem and the processing unit, the future action being scheduled for a future time adjusted with a latency value which represents a latency in powering up the at least one of the subsystem or the processing unit from a reduced power state and wherein the power controller is configured to supply power to the at least one of the subsystem or the processing unit in response to the future time as adjusted by the latency value.

A data processing system on a monolithic semiconductor substrate which provides a system on a chip (SOC), the data processing system comprising:

• a general purpose processing unit;
• a graphics processing unit;
• at least one peripheral interface controller;
• at least one bus coupled to the general purpose processing unit, the graphics processing unit, and the at least one peripheral interface controller;
• a power controller coupled to at least the general purpose processing unit and the graphics processing unit, the power controller being configured to turn power off for the general purpose processing unit in response to a first state of an instruction queue of the general purpose processing unit, and the power controller being configured to turn power off for the graphics processing unit in response to a second state of an instruction queue of the graphics processing unit.