Back to results
US 2008/0168263 A1Published application
Branch target buffer and method of use
AssigneeSamsung Electronics Co., Ltd.
InventorGi Ho Park
Life of this patent
Estimating the term…
Abstract
A branch target buffer (BTB) storing a data entry related to a branch instruction is disclosed. The BTB conditionally enables access to the data entry in response to a word line gating circuit associated with a word line in the BTB. The word line gating circuit stores a word line gating value derived from branch history data related to the instruction. Additionally, a branch prediction unit and a processor incorporating the BTB are disclosed, along with methods for operating the BTB.
Claims9
A processor, comprising:
- an instruction fetch unit to receive an instruction and provide a corresponding instruction address;
- a branch prediction unit to receive the instruction address and provide a predicted address to the instruction fetch unit;
- and,
- an instruction decoder/execution unit to receive the instruction, provide a decoded instruction, and provide an updated address in response to execution of the decoded instruction;
- wherein the branch prediction unit comprises:
- a branch history unit to store branch history data;
- branch prediction logic to receive the instruction address and the updated address, to provide the predicted address, and to update the branch history data;
- and,
- a branch target buffer to receive the instruction address and output a data entry, the branch target buffer comprising:
- a memory array comprising gated word lines, each gated word line connected to a corresponding word line gating circuit comprising a memory circuit storing a word line gating value derived from the branch history data.
7 more elements
Dependencies are inferred from the claim text.