Method and Apparatus for Self-Healing Symmetric Multi-Processor System Interconnects

A computer program product comprising:

• a computer usable medium having computer usable program code for symmetric multiprocessor interconnects, the computer program product comprising:
• computer usable program code for identifying functional communication connections between each processor in a plurality of processors on a multiprocessor to form identified functional communication connections;
• computer usable program code for mapping every functional communication connection between any two processors in the plurality of processors, based on the identified functional communication connections to form an interconnect matrix;
• computer usable program code for creating a path map using the interconnect matrix, wherein the path map comprises a sequence of communication connections between the plurality of processors;
• and
• computer usable program code for initializing the plurality of processors using the path map.

An apparatus for managing symmetric multiprocessor interconnects, the apparatus comprising:

• a computing device, the computing device comprising:
• a bus;
• a storage device connected to the bus, wherein the storage device contains a computer usable program product;
• and
• a plurality of processors, wherein at least one processor in the plurality of processors executes the computer usable program code to identify functional communication connections between each processor in a plurality of processors on a multiprocessor in an output file;
• generate an interconnect matrix based on the output file, wherein an interconnect matrix is a map of every functional communication connection between any two processors in a plurality of processors;
• create a path map based on the interconnect matrix, wherein a path map is a sequence of communication connections between a plurality of processors;
• and initialize the plurality of processors in accordance with the path map.

A multiprocessor, the multiprocessor comprising:

• an interconnect bus;
• a plurality of processors;
• a memory;
• and
• a controller, wherein the controller identifies functional communication connections between each processor in the plurality of processors in an output file in the memory;
• generates an interconnect matrix based on the output file, wherein an interconnect matrix is a map of every functional communication connection between any two processors in a plurality of processors;
• creates a path map based on the interconnect matrix, wherein a path map is a sequence of communication connections between a plurality of processors;
• and initializes the plurality of processors in accordance with the path map.