US 2008/0168241 A1 · REDUCING MEMORY ACCESS LATENCY FOR HYPERVISOR- OR SUPERVISOR-INITIATED MEMORY ACCESS REQUESTS

Abstract

A computer-implemented method, data processing system, and computer usable program code are provided for reducing memory access latency. A memory controller receives a memory access request and determines if an address associated with the memory access request falls within an address range of a plurality of paired memory address range registers. The memory controller determines if an enable bit associated with the address range is set to 1 in response to the address falling within one of the address ranges. The memory controller flags the memory access request as a high-priority request in response to the enable bit being set to 1 and places the high-priority request on a request queue. A dispatcher receives an indication that a memory bank is idle. The dispatcher determines if high-priority requests are present in the request queue and, if so, sends the earliest high-priority request to the idle memory bank.

Claims20

Dependent claims

A computer-implemented method for reducing memory access latency, the method comprising:

receiving, at a memory controller, a memory access request, wherein the memory access request includes an address;
determining if the address falls within an address range of a plurality of paired memory address range registers;
responsive to the address falling within one of the address range of the plurality of paired memory address range registers, determining if an enable bit is set to 1, wherein the enable bit is associated with the address range within which the address falls;
responsive to the enable bit being set to 1, flagging the memory access request as a high-priority request;
and
placing the high-priority request on a request queue.

3 more elements

A data processing system comprising:

a bus system;
a communications system connected to the bus system;
a memory connected to the bus system, wherein the memory includes a set of instructions;
and
a memory controller connected to the bus system, wherein the memory controller executes the set of instructions to receive a memory access request, wherein the memory access request includes an address;
determine if the address falls within an address range of a plurality of paired memory address range registers;
determine if an enable bit is set to 1 in response to the address falling within one of the address range of the plurality of paired memory address range registers, wherein the enable bit is associated with the address range within which the address falls;
flagging the memory access request as a high-priority request in response to the enable bit being set to 1;
and place the high-priority request on a request queue.

6 more elements

A computer program product comprising:

a computer usable medium including computer usable program code for reducing memory access latency, the computer program product including:
computer usable program code for receiving a memory access request, wherein the memory access request includes an address;
computer usable program code for determining if the address falls within an address range of a plurality of paired memory address range registers;
computer usable program code for determining if an enable bit is set to 1 in response to the address falling within one of the address range of the plurality of paired memory address range registers, wherein the enable bit is associated with the address range within which the address falls;
computer usable program code for flagging the memory access request as a high-priority request in response to the enable bit being set to 1;
and
computer usable program code for placing the high-priority request on a request queue.

4 more elements

Dependencies are inferred from the claim text.

Reducing memory access latency for hypervisor- or supervisor-initiated memory access requests

Life of this patent

Reducing memory access latency for hypervisor- or supervisor-initiated memory access requests

Life of this patent

Abstract

Claims20