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AssigneeInternational Business Machines Corporation
InventorsStephen LaRoux Blinick, Yu-Cheng Hsu, Lucien Mirabeau, Ricky Dean Rankin, Cheng-Chung Song
Estimating the term…
In managing multiprocessor operations, a first processor repetitively reads a cache line wherein the cache line is cached from a line of a shared memory of resources shared by both the first processor and a second processor. Coherency is maintained between the shared memory line and the cache line in accordance with a cache coherency protocol. In one aspect, the repetitive cache line reading occupies the first processor and inhibits the first processor from accessing the shared resources. In another aspect, upon completion of operations by the second processor involving the shared resources, the second processor writes data to the shared memory line to signal to the first processor that the shared resources may be accessed by the first processor. In response, the first processor changes the state of the cache line in accordance with the cache coherency protocol and reads the data written by the second processor. Other embodiments are described and claimed.
A system, comprising:
An article of manufacture, comprising at least one of a hardware device having hardware logic, and a computer readable storage medium having code, enabled to be executed by a system to perform operations, wherein the system has a first processor having a cache, a second processor, and a plurality of shared resources including a shared memory wherein a line of said shared memory is cached in a line of said first processor cache and coherency is maintained between said shared memory line and said cache line in accordance with a cache coherency protocol, and wherein the operations comprise:
Dependencies are inferred from the claim text.