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US 2008/0168231 A1Published application
Memory with shared write bit line(s)
AssigneeFreescale Semiconductor, Inc.
InventorRAVINDRARAJ RAMARAJU
Life of this patent
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Abstract
A memory includes at least one write bit line and a plurality of memory cells. The at least one write bit line is configured to carry a write bit signal. The plurality of memory cells are arranged in a column and are configured to be selectively coupled to the at least one write bit line. The plurality of memory cells are configured to be selectively read or written in a first phase of a cycle and selectively read or written in a second phase of the cycle using the at least one write bit line.
Claims20
A memory, comprising:
- at least one write bit line configured to carry a write bit signal;
- and
- a plurality of memory cells, wherein the plurality of memory cells are arranged in a column and are configured to be selectively coupled to the at least one write bit line, and wherein each of the plurality of memory cells are configured to be selectively read or written in a first phase of a cycle and selectively read or written in a second phase of the cycle using the at least one write bit line.
A cache subsystem, comprising:
- a cache memory;
- a tag memory, comprising:
- a plurality of tag cells arranged in tag cell groups and configured to store a plurality of multiple bit tags, wherein each of the plurality of multiple bit tags identify a respective line of the cache memory;
- and
- a plurality of status cells, wherein at least one of the plurality of status cells is associated with each respective one of the tag cell groups, and wherein each of the plurality of status cells are configured to be written to in a first phase of a cycle and written in a second phase of the cycle using shared write bit lines;
- and
- a cache controller coupled to the cache memory and the tag memory.
4 more elements
A method, comprising:
- reading or writing a first memory cell in a first phase of a cycle using at least one write bit line;
- and
- reading or writing a second memory cell using the at least one write bit line during a second phase of the cycle.
A memory, comprising:
- a first write bit line configured to carry a first write bit signal;
- a second write bit line configured to carry a second write bit signal that is a complement of the first write bit signal;
- a plurality of memory cells, wherein the plurality of memory cells are arranged in a column and are configured to be selectively coupled to the first and second write bit lines, and wherein each of the plurality of memory cells are configured to be selectively written in a first phase of a cycle and selectively written in a second phase of the cycle using the first and second write bit lines;
- a multiplexer including a first input, a second input and an output, wherein the first input of the multiplexer is configured to receive first data for the first phase of the cycle and the second input of the multiplexer is configured to receive second data for the second phase of the cycle, and wherein the output of the multiplexer is configured to provide the first data during the first phase of the cycle and the second data during the second phase of the cycle;
- a first inverter including an input and an output;
- and
- a second inverter including an input and an output, wherein the input of the first inverter is coupled to the output of the multiplexer and the output of the first inverter is coupled to the input of the second inverter and the first write bit line, and wherein the output of the second inverter is coupled to the second write bit line.
4 more elements
Dependencies are inferred from the claim text.