Dual Antenna System Having One Phase Lock Loop

A receiver circuit comprising:

• a first antenna and a second antenna;
• a first receive path comprising a first mixer that is coupled to receive a signal from the first antenna;
• a second receive path comprising a second mixer that is coupled to receive a signal from the second antenna;
• and
• a Voltage Controlled Oscillator (VCO) coupled to receive a Phase Lock Loop (PLL) signal and provide a first output signal and a second output signal respectively to the first mixer and the second mixer;
• wherein the VCO is separated from the first mixer and the second mixer respectively by a first differential buffer and a second differential buffer.

A direct conversion circuit comprising:

• a first antenna and a second antenna;
• a first receive path comprising a first mixer that is coupled to receive a signal from the first antenna;
• a second receive path comprising a second mixer that is coupled to receive a signal from the second antenna;
• and
• a Voltage Controlled Oscillator (VCO) providing In-phase (I) and Quadrature (Q) signals to the first mixer and the second mixer;
• wherein the first receive path and the second receive path are integrated together on a same device, operate at a same frequency, and are active together, and
• wherein the VCO is separated from the first mixer and the second mixer respectively by first differential buffer and a second differential buffer.

A system comprising:

• a first antenna and a second antenna;
• a direct conversion receiver comprising a first receive chain and a second receive chain respectively coupled to receive signals from the first antenna and the second antenna, wherein the first receive chain and the second receive chain are integrated together on a same device and operate at a same frequency and are active together;
• a first Analog-To-Digital Converters (ADC) and a second ADC to respectively receive the frequency down-converted signals from the first receive chain and the second receive chain;
• and
• a first filter and a second filter respectively coupled to the first ADC and the second ADC to provide digital data to the processor.
• wherein the first ADC and the second ADC are double clocked and multiplexed so that the first ADC and the second ADC and corresponding first filter and second filter are used for two receive paths.

A method comprising:

• receiving a first signal at a first antenna in a first receive path;
• receiving a second signal at a second antenna in a second receive path integrated separately from the first receive path;
• providing a Phase Lock Loop (PLL) signal to a Voltage Controlled Oscillator (VC)) in the first receive path;
• mixing the VCO output signal with the first signal to generate a first mixed signal;
• providing the VCO output signal to terminals external to the first receive path;
• and
• mixing the signal provided to the terminals external to the first receive path with the signal received by the second antenna in the second receive path to generate a second mixed signal.

A method comprising:

• receiving a first signal at a first antenna in a first receive chain;
• receiving a second signal at a second antenna in a second receive chain;
• generating first and second frequency down converted signals using the first and second receive chains respectively;
• receiving the first and second frequency down-converted signals at first and second doubled clocked and multiplexed Analog-to-Digital Converter (ADCs) respectively;
• digitizing the first and second frequency down-converted signals using the first and second double clocked and multiplexed ADCs respectively;
• and
• filtering the digitized first and second frequency down-converted signals.