Semiconductor transistors with contact holes close to gates

A structure formation method, comprising:

• providing a structure including:
• (a) a semiconductor layer including (i) a channel region and (ii) first and second source/drain (S/D) regions, wherein the channel region is disposed between and electrically coupled to the first and second S/D regions,
• (b) a gate dielectric region in direct physical contact with the channel region via an interfacing surface which defines a reference direction perpendicular to the interfacing surface, wherein the gate dielectric region is above the channel region in the reference direction,
• (c) a gate region in direct physical contact with the gate dielectric region, wherein the gate dielectric region is sandwiched between and electrically insulates the gate region and the channel region, and
• (d) a hard cap region on the gate region;
• forming a protection umbrella region from the hard cap region such that the gate region is completely in a shadow of the protection umbrella region, wherein the shadow of the protection umbrella region comprises a space shielded by the protection umbrella region from an imaginary light point source (i) directly above the protection umbrella region in the reference direction and (ii) infinitely far from the protection umbrella region;
• blanket depositing an inter-level dielectric (ILD) layer on the structure after said forming the protection umbrella region is performed;
• creating a contact hole in the ILD layer directly above the second S/D region and aligned with an edge of the protection umbrella region, wherein the contact hole is physically isolated from the gate region by the ILD layer;
• and
• filling the contact hole with an electrically conducting material.