LDMOS device and method

A semiconductor device, comprising:

• a semiconductor substrate having a lightly doped region of a first conductivity type and first dopant concentration extending to a surface;
• a first well of said first conductivity type and second dopant concentration larger than said first dopant concentration, in said lightly doped region and with a first edge extending to said surface;
• a second well of a second, opposite, conductivity type and third dopant concentration larger than said first dopant concentration, in and forming a PN junction with said lightly doped region and spaced apart from said first well, wherein said PN junction extends to said surface;
• a gate electrode overlying and insulated from said surface, having a left edge substantially aligned with said first edge and a rightward extension over a portion of said lightly doped region at least to said second well;
• a HALO implant region of said first conductivity type and a fourth dopant concentration extending beyond said left edge toward said second well;
• a source region of said second conductivity type and fifth dopant concentration at least partly in said first well communicating with said HALO implant region;
• and
• a drain region of said second conductivity type and sixth dopant concentration in said second well and spaced apart from said gate electrode.

A method for forming an LDMOS device, comprising:

• providing a semiconductor substrate having a first region of first conductivity type and first dopant concentration in the range of about 1E14 cm−3 to 5E15 cm−3, extending to a surface;
• forming first and second wells in the first region, spaced apart by a portion of the first region and having, respectively, first and second conductivity types and second and third dopant concentrations and first and second lateral edges, wherein the first and second lateral edges extend to the surface and the second conductivity type is opposite the first conductivity type;
• forming a gate electrode insulated from the surface, overlying the portion of the first region and having a left lateral edge substantially aligned with the first edge and a right lateral edge located at or beyond the second edge;
• using the gate electrode as at least a partial mask, implanting impurities at an angle to form a HALO pocket beneath the surface overlapping the first edge;
• and
• implanting source and drain regions of the second conductivity type, the source region at least partly in the first well and the drain region located in the second well a first distance from the right lateral edge of the gate electrode.