Method for reducing overlap capacitance in field effect transistors
AssigneeInternational Business Machines Corporation
InventorsHuilong Zhu, Oleg Gluschenkov
Life of this patent
Estimating the term…
Abstract
A method for forming a field effect transistor (FET) device includes forming a gate conductor over a semiconductor substrate; forming a source region, the source region having a source extension that overlaps and extends under the gate conductor; and forming a drain region, the drain region having a drain extension that overlaps and extends under the gate conductor at selected locations along the width of the gate; and the drain region further comprising a plurality of recessed areas corresponding to areas where the drain extension does not overlap and extend under the gate conductor, wherein the plurality of recessed areas is formed only in the drain region.
Claims8
A method for forming a field effect transistor (FET) device, the method comprising:
- forming a gate conductor over a semiconductor substrate;
- forming a source region, said source region having a source extension that overlaps and extends under said gate conductor;
- and
- forming a drain region, said drain region having a drain extension that overlaps and extends under said gate conductor at selected locations along the width of said gate;
- and
- said drain region further comprising a plurality of recessed areas corresponding to areas where said drain extension does not overlap and extend under said gate conductor, wherein said plurality of recessed areas is formed only in said drain region.
The method of claim 7, wherein said plurality of recessed areas only in said drain region are formed by performing a selective etch of said semiconductor substrate.
A method for forming a field effect transistor (FET) device, the method comprising:
- forming a gate conductor over a semiconductor substrate;
- forming a source region, said source region having a source extension that overlaps and extends under said gate conductor;
- and
- forming a drain region, said drain region having a drain extension that overlaps and extends under said gate conductor at selected locations along the width of said gate;
- and
- said drain region further comprising a plurality of recessed areas corresponding to areas where said drain extension does not overlap and extend under said gate conductor, wherein said plurality of recessed areas are formed by performing a selective etch of said semiconductor substrate;
- and
- implanting portions of said semiconductor substrate corresponding to said plurality of recessed areas with a neutral dopant selected to increase the etch rate of doped areas of said substrate with respect to undoped areas of said substrate.
Dependencies are inferred from the claim text.