Method of Forming Trench Gate FETs with Reduced Gate to Drain Charge

A method of forming a field effect transistor, comprising:

• forming trenches in a semiconductor region of a first conductivity type;
• forming a first insulating layer along opposing sidewalls of each trench;
• filling each trench with a dielectric fill material having a higher etch rate than the first insulating layer;
• simultaneously etching the dielectric fill material and the first insulating layer such that:
• (i) an upper portion of the first insulating layer is completely removed from along an upper portion of the opposing sidewall of each trench and a remaining lower portion of the first insulating layer has a tapered edge, and (ii) a portion of the dielectric fill material remains in each trench;
• and
• forming a second insulating layer at least along upper portions of the opposing sidewalls of each trench where the first dielectric layer was completely removed.

A method of forming a field effect transistor, comprising:

• forming trenches in a semiconductor region of a first conductivity type;
• forming a well region of a second conductivity type in the semiconductor region;
• forming source regions of the first conductivity type in the well region such that channel regions defined by a spacing between the source regions and a bottom surface of the well region are formed in the well region along opposing sidewalls of the trenches, and a doping concentration in the channel regions decreases from a maximum concentration in the direction from the source regions toward a bottom surface of the well region;
• forming a gate dielectric layer having a non-uniform thickness along the opposing sidewalls of the trenches such that a thickness of the gate dielectric layer increases in a substantially linear manner from a point below the maximum concentration in the direction from the source regions to the bottom surface of the well region;
• and
• forming a gate electrode in each trench.