US 2008/0166843 A1Published application

Isolation regions for semiconductor devices and their formation

AssigneeMicron Technology, Inc.

InventorMark S. Korber

Life of this patent

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Abstract

A hard mask layer is formed and patterned overlying a semiconductor substrate of a semiconductor device. The patterned hard mask layer exposes two or more areas of the substrate for future isolation regions of the semiconductor device. Portions of the substrate are removed in the areas for future isolation regions, thereby forming two or more trenches. A second mask layer is formed overlying a first portion of the hard mask layer and at least one first trench, and a second portion of the hard mask layer and at least one second trench are left uncovered. Additional substrate material is removed from the at least one second trench so that the at least one second trench is deeper than the at least one first trench. The hard mask layer and the second mask are removed substantially concurrently.

Claims27

Dependent claims

A method of forming a memory device, comprising:

forming a first dielectric layer on a semiconductor substrate;
forming a protective cap layer overlying the first dielectric layer;
forming and patterning a hard mask layer overlying the protective cap layer, the patterned hard mask layer exposing two or more areas of the protective cap layer, the first dielectric layer, and the substrate for future isolation regions of the memory device;
removing portions of the protective cap layer, the first dielectric layer and the substrate in the areas for future isolation regions, thereby forming two or more trenches;
forming a second mask layer overlying a first portion of the hard mask layer and at least one first trench in a memory array portion of the memory device, leaving a second portion of the hard mask layer and at least one second trench uncovered in a periphery of the memory device;
removing additional substrate material from the at least one second trench so that the at least one second trench is deeper than the at least one first trench;
removing the hard mask layer and the second mask layer substantially concurrently;
filling the at least one first trench and the at least one second trench with a dielectric material to respectively form at least one first isolation region in the memory array portion and at least one second isolation region in the periphery;
removing the protective cap layer;
forming a second dielectric layer overlying the substrate and on the at least one first isolation region and the at least one second isolation region;
and
forming a first conductive layer overlying the second dielectric layer.

9 more elements

A method of forming a memory device, comprising:

forming a first dielectric layer on a semiconductor substrate;
forming a first conductive layer on the dielectric layer;
forming a protective cap layer on the conductive layer;
forming a hard mask layer overlying the protective cap layer;
forming a second mask layer overlying the hard mask layer for exposing two or more areas of the hard mask layer;
removing the exposed two or more areas of the hard mask layer for exposing two or more areas of the protective cap layer, the conductive layer, the dielectric layer, and the substrate for future isolation regions of the memory device;
removing the second mask layer;
removing portions of the protective cap layer, the dielectric layer, the conductive layer, and the substrate in the areas for future isolation regions, thereby forming two or more trenches;
forming a third mask layer overlying a first portion of the hard mask layer and at least one first trench in a memory array portion of the memory device, leaving a second portion of the hard mask layer and at least one second trench uncovered in a periphery of the memory device;
removing additional substrate material from the at least one second trench so that the at least one second trench is deeper than the at least one first trench;
stripping the hard mask layer and the third mask layer substantially concurrently;
filling the at least one first trench and the at least one second trench with a dielectric material to respectively form at least one first isolation region in the memory array portion and at least one second isolation region in the periphery;
removing the protective cap layer to expose the first conductive layer;
forming a second dielectric layer on the first conductive layer and on the at least one first isolation region and the at least one second isolation region;
and
forming a second conductive layer on the second dielectric layer.

13 more elements

A method of forming a memory device, comprising:

forming a first dielectric layer on a semiconductor substrate;
forming a first conductive layer on the dielectric layer;
forming a protective cap layer on the conductive layer;
forming a carbon mask layer overlying the protective cap layer;
forming a first photo-resist mask layer overlying the carbon mask layer for exposing two or more areas of the carbon mask layer;
removing the exposed two or more areas of the carbon mask layer for exposing two or more areas of the protective cap layer, the conductive layer, the dielectric layer, and the substrate for future isolation regions of the memory device;
removing the first photo-resist mask layer;
removing portions of the protective cap layer, the dielectric layer, the conductive layer, and the substrate in the areas for future isolation regions, thereby forming two or more trenches;
forming a second photo-resist mask layer overlying a first portion of the carbon mask layer and at least one first trench in a memory array portion of the memory device, leaving a second portion of the carbon mask layer and at least one second trench uncovered in a periphery of the memory device;
removing additional substrate material from the at least one second trench so that the at least one second trench is deeper than the at least one first trench;
removing the carbon mask layer and the second photo-resist mask layer substantially concurrently;
filling the at least one first trench and the at least one second trench with a dielectric material to respectively form at least one first isolation region in the memory array portion and at least one second isolation region in the periphery;
removing the protective cap layer to expose the first conductive layer;
forming a second dielectric layer on the first conductive layer and on the at least one first isolation region and the at least one second isolation region;
and
forming a second conductive layer on the second dielectric layer.

13 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/050,284Filed 18 Mar 2008
Priority: 26 Jan 2005
Published: 10 Jul 2008
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10W 10/17
Isolation regions comprising dielectric materials: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
H10B 41/40
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the peripheral circuit region
H10B 41/42
Characterised by the peripheral circuit region: simultaneous manufacture of periphery and memory cells
H10W 10/0143
Using trench refilling with dielectric materials, e.g. shallow trench isolations: comprising concurrently refilling multiple trenches having…

Family

Application11/043,838Division · filed 26 Jan 2005
Application12/050,284Division
US 2006/0166437 A1Published application
US 7,344,942 B2Related patent
US 7,670,907 B2Related patent
US 2008/0166843 A1This patent

From the US filing history. Foreign family members aren’t listed.