Power MOSFET wafer level chip-scale package
OwnerTao Feng, Ming Suninventors
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Abstract
A power MOSFET wafer level chip-scale packaging method is disclosed. The method includes the steps of electroless plating a wafer backside and a plurality of contact pads on a wafer front side and forming solder balls on the plated plurality of contact pads before dicing the wafer into a plurality of power MOSFET dies. In an alternative embodiment, the method includes the steps of providing a permanent protective layer on a wafer backside, electroless plating a plurality of contact pads on a wafer front side, and forming solder balls on the plated plurality of contact pads before dicing the wafer into a plurality of power MOSFET dies.
Claims19
A method of manufacturing a power MOSFET wafer level chip-scale package comprising the steps of:
- electroless Ni plating a wafer backside and a plurality of contact pads on a wafer front side;
- and
- forming solder balls on the plated plurality of contact pads.
A method of manufacturing a power MOSFET wafer level chip-scale package comprising the steps of:
- providing a permanent protective layer on a wafer backside;
- electroless Ni plating a plurality of contact pads on a wafer front side;
- and
- forming solder balls on the plated plurality of contact pads.
A method of manufacturing a power MOSFET wafer level chip-scale package comprising the steps of:
- providing a permanent dummy substrate on a wafer backside;
- under bump metallizing a plurality of contact pads on a wafer front side through sputtering and electrolytic plating;
- and
- forming solder balls on the plated plurality of contact pads.
Dependencies are inferred from the claim text.