Thin film transistor array panel and method for manufacturing the same
AssigneeSamsung Electronics Co., Ltd.
InventorsBeom-Seok Cho, Yang-Ho Bae, Je-Hun Lee, Chang-Oh Jeong
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Abstract
The present invention provides a TFT array panel and a manufacturing method of the same, which has signal lines including a lower layer of an Al containing metal and an upper layer of a molybdenum alloy (Mo-alloy) comprising molybdenum (Mo) and at least one of niobium (Nb), vanadium (V), and titanium (Ti). Accordingly, undercut, overhang, and mouse bites which may arise in an etching process, are prevented, and TFT array panels that have signal lines having low resistivity and good contact characteristics are provided.
Claims8
A manufacturing method of a thin film transistor array panel, comprising:
- forming a gate line on an insulating substrate, the gate line having a first layer of an Al containing metal and a second layer of a Mo-alloy comprising molybdenum (Mo) and at least one of niobium (Nb), vanadium (V), and titanium (Ti), the gate line having a gate electrode;
- depositing a gate insulating layer, a semiconductor layer, and a ohmic contact layer on the gate line in sequence;
- patterning the semiconductor layer and the ohmic contact layer;
- forming a drain electrode and a data line having a source electrode on the gate insulating layer and the ohmic contact layer, the drain electrode facing the source electrode with a predetermined gap;
- forming a passivation layer having a contact hole exposing the source electrode on the data line and the drain electrode;
- and
- forming a pixel electrode connected to the drain electrode through the contact hole on the passivation layer.
A manufacturing method of a thin film transistor array panel, comprising:
- forming a gate line on an insulating substrate;
- depositing a gate insulating layer, a semiconductor layer, and a ohmic contact layer on the gate line in sequence;
- patterning the semiconductor layer and the ohmic contact layer;
- forming a drain electrode and a data line having a source electrode on the gate insulating layer and the ohmic contact layer, the data line and the drain electrode having a first layer of a Mo containing metal, a second layer of an Al containing metal, and a third layer of a Mo containing metal, at least one of the first and third layers comprising a Mo-alloy including molybdenum (Mo) and at least one of niobium (Nb), vanadium (V), and titanium (Ti);
- forming a passivation layer having a contact hole exposing the source electrode on the data line and the drain electrode;
- and
- forming a pixel electrode connected to the drain electrode through the contact hole on the passivation layer.
Dependencies are inferred from the claim text.