Wireless receiver
AssigneeKabushiki Kaisha Toshiba
InventorMasafumi Takahashi
Life of this patent
Estimating the term…
Abstract
A bitstream analysis circuit, generates a reference clock control data. A reference clock DPLL receives a system clock signal and reference clock control data from the analysis circuit and generates a reference clock signal. The reference clock DPLL comprises a 1/n frequency dividing circuit for frequency-dividing the system clock signal, and a 1/(n+1) frequency dividing circuit for frequency-dividing the system clock signal. A register stores data to set frequency dividing ratios of both frequency dividing circuits. A mixing ratio set register stores data to set a mixing ratio between output clock signals from both frequency dividing circuits and a mixing circuit, and mixes the output clock signals from both frequency dividing circuits at a mixing ratio in response to the data in the mixing ratio setting register.
Claims20
A wireless receiver comprising:
- a bitstream analysis circuit which receives a bitstream signal including audio/video data and time data, receives a reference clock signal, detects and outputs the audio/video data and the time data in the bitstream by analyzing the bitstream signal, and outputs reference clock control data on the basis of the time data;
- and
- a first digital phase-locked loop circuit which receives a system clock signal and the reference clock control data, and generates the reference clock signal to supply it to the bitstream analysis circuit.
A digital broadcasting receiver comprising:
- a bitstream analysis circuit which receives an MPEG-2 TS bitstream signal included in a digital broadcasting signal, a reference clock signal, detects and outputs audio/video data and time data in the bitstream by analyzing the received signals and outputs reference clock control data on the basis of the time data;
- a first digital phase-locked loop circuit which receives a system clock signal and the reference clock control data and generates the reference clock signal with a prescribed frequency to supply it to the bitstream analysis circuit;
- a reference time generation circuit which receives the system clock signal and the reference clock signal, counts the reference clock signal and generates the reference time signal synchronized with the reference clock signal at every specified interval;
- a second digital phase-locked loop circuit which receives the system clock signal and the reference time signal and generates an audio master clock signal to be used at the time of audio signal reproduction in synchronization with the reference time signal;
- a third digital phase-locked loop circuit which receives at least the system clock signal and generates a video master clock signal to be used at the time of video signal reproduction;
- and
- an audio/video decoder which receives audio/video data output from the bitstream analysis circuit, the audio master clock signal and the video master clock signal, decodes the audio/video data and reproduces an audio signal and a video signal in synchronization with the audio master clock signal and the video master clock signal.
A portable type digital broadcasting receiver comprising:
- a bitstream analysis circuit which receives an MPEG-2 TS bitstream signal included in a digital broadcasting signal, a reference clock signal, detects and outputs audio/video data and time data in the bitstream by analyzing the received signals and outputs reference clock control data on the basis of the time data;
- a first digital phase-locked loop circuit which receives a system clock signal and the reference clock control data, the first digital phase-locked loop circuit generates the reference clock signal with a prescribed frequency to supply it to the bitstream analysis circuit;
- a reference time generation circuit which receives the system clock signal and the reference clock signal, counts the reference clock signal and generates the reference time signal synchronized with the reference clock signal at every specified time;
- a second digital phase-locked loop circuit which receives the system clock signal and the reference time signal and generates an audio master clock signal to be used at the time of audio signal reproduction in synchronization with the reference time signal;
- a third digital phase-locked loop circuit which receives the system clock signal and generates a video master clock signal to be used at the time of video signal reproduction;
- and
- an audio/video decoder which receives audio/video data output from the bitstream analysis circuit, the audio master clock signal and the video master clock signal, decodes the audio/video data and reproduces an audio signal and a video signal in synchronization with the audio master clock signal and the video master clock signal;
- a display device which receives the video signal reproduced by the audio/video decoder to display images;
- and
- a sound output device which receives the audio signal reproduced by the audio/video decoder to output sounds.
Dependencies are inferred from the claim text.