Digital clock generating circuit and method of operation

A method for generating a reference clock signal, the method comprising:

• producing an output that is configurable to be at either one of a first frequency and a second frequency, the second frequency being different than the first frequency;
• setting the output to operate at the second frequency,
• determining a number of pulses produced in the output at the second frequency that differs from a number of pulses that would have been produced in the output at the first frequency, within a time period specified by the constant timing reference;
• and
• removing, in response to setting the output to change from the second frequency to the first frequency, the number of pulses accumulated.

A digital clock generation circuit, comprising:

• a digital clock configurable to produce an output at either one of a first frequency and a second frequency, the second frequency being different than the first frequency;
• a clock control circuit controlling the digital clock and selectively setting the digital clock to produce the output at one of the first frequency and the second frequency;
• a constant timing reference producing a non-interrupted timing interval that is independent of the frequency being generated by the clock generator, the timing interval comprising an integer number of pulses produced by the digital clock at the second frequency that differs from a number of pulses that would have been produced by the digital clock at the first frequency during the timing interval;
• an excess pulse counter, communicatively coupled to the clock control circuit, the constant timing reference, and the digital clock, the excess pulse counter determining a number of pulses produced by the digital clock at the second frequency that differs from the number of pulses that would have been produced by the digital clock at the first frequency during the timing interval;
• and
• an output phase correction circuit, communicatively coupled to the digital clock, the excess pulse counter, and the clock control circuit, the output phase correction circuit removing, in response to the clock control circuit commanding the digital clock to change from producing an output at the second frequency to producing an output at the first frequency, the number of pulses from the output that were counted by the excess pulse counter.