US 2008/0165610 A1 · SEMICONDUCTOR MEMORY DEVICE CAPABLE OF SYNCHRONOUS/ASYNCHRONOUS OPERATION AND DATA INPUT/OUTPUT METHOD THEREOF

Abstract

A semiconductor memory device capable of synchronous/asynchronous operation and data input/output method thereof are provided. The semiconductor memory device includes a memory cell array, a peripheral circuit configured to write data to a cell in the memory cell array and to read data from the cell, and a bypass control unit configured to control a late write operation and a bypass operation of the peripheral circuit according to mode conversion of the semiconductor memory device. Accordingly, data coherency can be maintained. In addition, dummy cycle time that may occur during the mode conversion can be prevented by generating a mode conversion signal only in response to toggling of a clock signal.

Claims18

Dependent claims

A semiconductor memory device that operates in a first mode and a second mode, the semiconductor memory device comprising:

a memory cell array comprising a plurality of memory cells arrayed in columns and rows in a matrix;
a peripheral circuit coupled to the memory cell array and configured to write data to the memory cell array and to read data from the memory cell array;
and
a bypass control unit coupled to the peripheral unit, the bypass control unit configured to enable a late write operation and a bypass operation of the peripheral circuit when the semiconductor memory device operates in the first mode and to disable the late write operation and the bypass operation of the peripheral circuit when the semiconductor memory device operates in the second mode.

1 more element

Dependencies are inferred from the claim text.

Semiconductor memory device capable of synchronous/asynchronous operation and data input/output method thereof

Life of this patent

Semiconductor memory device capable of synchronous/asynchronous operation and data input/output method thereof

Life of this patent

Abstract

Claims18