Repairing integrated circuit memory arrays
AssigneeArm Limited
InventorsAnurag Mittal, Jungtae Kwon
Life of this patent
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Abstract
A memory array 2 has an address decoder 12 responsive to a repair signal to operate either in a normal mode or a repair mode. In the normal mode a data bit is stored within a single memory cell 6. In the repair mode a data bit is stored within multiple memory cells 6 of a common column of memory cells sharing bit lines 8. This provides increased defect resistance when operating in the repair mode at the cost of reduced memory capacity.
Claims33
An integrated circuit comprising:
- at least one array of memory cells having a plurality of rows of memory cells and a plurality of columns of memory cells;
- a plurality of bit lines, each of said plurality of bit lines being coupled to a respective column of said memory cells;
- a plurality of word lines carrying respective word line signals, each of said plurality of word lines being coupled to a respective row of said memory cells to control coupling of said respective row of memory cells to said plurality of bit lines so as to provide access to data bits stored therein;
- an address decoder responsive to input memory addresses to generate said word line signals;
- and
- repair control circuitry responsive to a repair signal to control said address decoder during a memory access operation to an memory input address such that:
- in a normal mode, a single row of memory cells is selected for access by one word line signal on one word line such that for each column of memory cells one memory cell is coupled to a corresponding bit line of said plurality of bit lines to provide access to a data bit as stored within said one memory cell;
- and
- in a repair mode, a plurality of rows of memory cells are selected for access by a plurality of word line signals on a plurality of word lines such that for each column of memory cells a plurality of memory cells are coupled to said corresponding bit line of said plurality of bit lines to provide access to said data bit as stored within said plurality of memory cells.
An integrated circuit comprising:
- at least one array of memory cell means having a plurality of rows of memory cell means and a plurality of columns of memory cell means;
- a plurality of bit line means, each of said plurality of bit line means being coupled to a respective column of said memory cell means;
- a plurality of word line means carrying respective word line signals, each of said plurality of word line means being coupled to a respective row of said memory cell means to control coupling of said respective row of memory cell means to said plurality of bit line means so as to provide access to data bits stored therein;
- address decoder means for generating said word line signals in response to input memory addresses;
- and
- repair control means for controlling said address decoder means during a memory access operation to an input memory address and a repair signal such that:
- in a normal mode, a single row of memory cell means is selected for access by one word line signal on one word line means such that for each column of memory cell means one memory cell means is coupled to a corresponding bit line means of said plurality of bit line means to provide access to a data bit as stored within said one memory cell means;
- and
- in a repair mode, a plurality of rows of memory cell means are selected for access by a plurality of word line signals on a plurality of word line means such that for each column of memory cell means a plurality of memory cell means are coupled to said corresponding bit line means of said plurality of bit line means to provide access to said data bit as stored within said plurality of memory cell means.
A method of operating an integrated circuit having at least one array of memory cells with a plurality of rows of memory cells and a plurality of columns of memory cells, a plurality of bit lines, each of said plurality of bit lines being coupled to a respective column of said memory cells, a plurality of word lines carrying respective word line signals, each of said plurality of word lines being coupled to a respective row of said memory cells to control coupling of said respective row of memory cells to said plurality of bit lines so as to provide access to data bits stored therein and an address decoder responsive to input memory addresses to generate said word line signals;
- said method comprising
- in response to a repair signal, controlling said address decoder during a memory access operation to an input memory address such that:
- in a normal mode, a single row of memory cells is selected for access by one word line signal on one word line such that for each column of memory cells one memory cell is coupled to a corresponding bit line of said plurality of bit lines to provide access to a data bit as stored within said one memory cell;
- and
- in a repair mode, a plurality of rows of memory cells are selected for access by a plurality of word line signals on a plurality of word lines such that for each column of memory cells a plurality of memory cells are coupled to said corresponding bit line of said plurality of bit lines to provide access to said data bit as stored within said plurality of memory cells.
Dependencies are inferred from the claim text.