Semiconductor memory device having sense amplifier operable as a semi-latch type and a full-latch type based on timing and data sensing method thereof

A semiconductor memory device comprising:

• a memory cell array including memory cells arranged in rows and columns;
• a first sense amplifier detecting and amplifying data of the memory cells coupled to the selected row through the columns;
• and
• a second sense amplifier detecting and amplifying data output from the first sense amplifier through a data bus,
• wherein the second sense amplifier is configured to operate in a semi-latch type mode for a first sensing period and to operate in a full-latch type mode for a second sensing period after the first sensing period.

A data sensing method of a semiconductor memory device having a memory cell array including memory cells arranged in rows and columns, the method comprising:

• sensing and amplifying data of the memory cells coupled to a selected row through the columns;
• sensing and amplifying the sensed and amplified data, which is output from a data bus for a first sensing period, in a semi-latch type mode;
• and
• sensing and amplifying the sensed and amplified data of the semi-latch type mode in a full-latch type mode for a second sensing period after the first sensing period.