Back to results
US 2008/0165602 A1Published application
Processor Instruction Cache with Dual-Read Modes
AssigneeMarvell World Trade Ltd.
InventorsSehat Sutardja, Jason T. Su, Hong-Yi Chen, Jason Sheu, Jensen Tjeng
Life of this patent
Estimating the term…
Abstract
A processor includes a cache memory. The cache memory includes an array of cells, word lines and bit lines. A control module enables a word line of the word lines to access a first cell in the enabled word line. The control module disables the word line and maintains the word line in a disabled state to access a second cell in the word line.
Claims47
A processor comprising:
- a cache memory that comprises:
- an array of cells;
- a plurality of word lines;
- and
- a plurality of bit lines;
- and
- a control module that enables a word line of said plurality of word lines to access a first cell in said word line, that disables said word line, and that maintains said word line in a disabled state to access a second cell in said word line.
4 more elements
A method comprising:
- providing a cache memory that comprises:
- an array of cells;
- a plurality of word lines;
- and
- a plurality of bit lines;
- enabling a word line of said plurality of word lines to access a first cell in said word line;
- disabling said word line;
- and
- maintaining said word line in a disabled state to access a second cell in said word line.
6 more elements
Dependencies are inferred from the claim text.