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US 2008/0165599 A1Published application
Design structure used for repairing embedded memory in an integrated circuit
OwnerKevin W. Gormaninventor
Life of this patent
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Abstract
A design structure for correcting embedded memory that has been identified as being defective by a memory controller. The address of the defective memory is provided by the memory controller to Built-In Test (BIST) logic in combination with a Built-In Redundancy Analyzer (BIRA) to replace the defective memory element with a redundant element.
Claims14
A design structure comprising:
- memory having memory elements and redundant memory elements;
- a memory controller that accesses the memory and detects a defective memory element;
- a built-in self test circuit that receives the address for the defective memory element and replaces the defective memory element with a redundant memory element.
A design structure for repairing embedded memory during operation of an integrated circuit, the design structure comprising:
- means for detecting a defective memory element with a memory controller;
- means for transmitting the address of the defective memory to a built-in self test circuit having an address generator that generates memory addresses during operation of the built-in self test circuit;
- means for accessing the defective memory element with the built-in self test circuit using the transmitted address instead of the generated addresses;
- means for reading data from the defective memory element and comparing the data with a value that will fail to match the data;
- means for replacing the defective memory element with a redundant memory element.
2 more elements
Dependencies are inferred from the claim text.