Semiconductor memory device with debounced write control signal

A semiconductor memory device having a memory cell array that stores data received through an input buffer in a memory region designated by an address signal in a write operation and outputs data from the memory region designated by the address signal through an output buffer in a read operation, and having an input-output control circuit that controls the input buffer and the output buffer according to externally generated signals including at least a write control signal, wherein:

• the output buffer generates a commencement signal having an active state and an inactive state, the active state indicating commencement of output;
• the input-output control circuit generates an internal enable signal having an active state and an inactive state, the active state commanding the output buffer to commence output;
• the semiconductor memory device comprises
• a mask generating circuit for generating a mask signal having an active state and an inactive state from the commencement signal, the mask signal becoming active at least as soon as the commencement signal becomes active and remaining active until after the commencement signal has become inactive;
• and
• a masking circuit for passing the write control signal to the input-output control circuit while the mask signal is inactive, and holding the write control signal input to the input-output control circuit in a write-disabling state while the mask signal is active;
• and
• the mask generating circuit comprises
• a first delay circuit for delaying the internal enable signal to generate a delayed enable signal;
• a second delay circuit for delaying the commencement signal to generate a delayed commencement signal;
• and
• a logic circuit for performing a logic operation on the delayed enable signal and the delayed commencement signal to generate the mask signal.