Semiconductor memory device and method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsKwun-soo Cheon, Chang-yong Lee, Won-kyung Chung
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Abstract
A semiconductor memory device and method thereof are provided. The example semiconductor memory device may include a memory cell array including a plurality of memory cells, an expected data generating unit receiving a plurality of initial expected data through at least one address pad during a memory operation and generating a plurality of expected data based on the plurality of initial expected data, the at least one address pad being separate from a data input/output pad and a parallel bit test circuit generating test result data based on a plurality of read data and the plurality of expected data.
Claims21
A semiconductor memory device, comprising:
- a memory cell array including a plurality of memory cells;
- an expected data generating unit receiving a plurality of initial expected data through at least one address pad during a memory operation and generating a plurality of expected data based on the plurality of initial expected data, the at least one address pad being separate from a data input/output pad;
- and
- a parallel bit test circuit generating test result data based on a plurality of read data and the plurality of expected data.
A parallel bit test method testing a semiconductor memory device including a memory cell array having a plurality of memory cells, comprising:
- receiving a plurality of initial expected data through at least one address pad during a memory operation, the at least one address pad being separate from a data input/output pad;
- generating a plurality of expected data based on the plurality of initial expected data;
- and
- generating test result data based on a plurality of read data and the plurality of expected data.
Dependencies are inferred from the claim text.