Semiconductor memory device, sense amplifier circuit and memory cell reading method
AssigneeSony Corporation
InventorsMakoto Kitagawa, Wataru Otsuka
Life of this patent
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Abstract
A semiconductor memory device includes: a memory cell; a sense line; and a sense amplifier circuit connected to the memory cell via the sense line. The sense amplifier circuit includes a differential sense amplifier, a pull-up section, a read gate transistor, and a threshold correction section.
Claims15
A semiconductor memory device, comprising:
- a memory cell;
- a sense line;
- and
- a sense amplifier circuit connected to the memory cell via the sense line;
- wherein
- the sense amplifier circuit includes
- a differential sense amplifier having first and second differential inputs and whose second differential input is supplied with a reference voltage,
- a pull-up section adapted to pull up the first differential input to a constant voltage,
- a read gate transistor connected between the sense line and the first differential input, and adapted to turn on if the sense line potential drops below an initial voltage in response to a cell current, and
- a threshold correction section adapted to generate a voltage corrected from the initial voltage by making or breaking a diode connection of a given transistor, the impact of whose threshold voltage on the sense line potential is to be eliminated, and also adapted to apply the corrected voltage to the control terminal of the read gate transistor.
A sense amplifier circuit adapted to detect the voltage of a sense line which varies according to a current flowing through the sense line when the sense line is in a potentially floating state following the application of a given initial voltage to this line, the sense amplifier circuit, comprising:
- a differential sense amplifier having first and second differential inputs and whose second differential input is supplied with a reference voltage;
- a pull-up section adapted to pull up the first differential input to a constant voltage;
- a read gate transistor connected between the sense line and the first differential input, and adapted to turn on if the sense line potential drops below an initial voltage in response to a cell current;
- and
- a threshold correction section adapted to generate a voltage corrected from the initial voltage by making or breaking a diode connection of a given transistor, the impact of whose threshold voltage on the sense line potential is to be eliminated, and also adapted to apply the corrected voltage to the control terminal of the read gate transistor.
A memory cell reading method operable to read stored data from a memory cell via a read gate transistor which is connected between a sense line and a sense node and which turns on if the sense line potential drops below an initial voltage in response to a cell current, the memory cell reading method, comprising the steps of:
- generating a voltage corrected from the initial voltage by making or breaking a diode connection of a given transistor, the impact of whose threshold voltage on the sense line potential is to be eliminated, applying the corrected voltage to the control terminal of the read gate transistor, and setting the sense line to the initial voltage to bring the line into a floating state;
- and
- detecting the change in the sense node potential which changes with change in a cell current by connecting the sense line, pulled up to a constant voltage, to the memory cell and comparing the change in the sense node potential with a reference voltage.
Dependencies are inferred from the claim text.