Method and system for a serial peripheral interface

A method for quadruple I/O data read in an integrated circuit which includes a memory device, a clock signal, a plurality of pins, and a configuration register, the configuration register including a wait cycle count, the method comprising:

• transmitting a read address to the memory device using a first pin, a second pin, a third pin, and a fourth pin concurrently, the read address being associated with a location in the memory device, the read address including at least a first address bit, a second address bit, a third address bit, and a fourth address bit, the first address bit being transmitted using the first pin, the second address bit being transmitted using the second pin, the third address bit being transmitted using the third pin, and the fourth address bit being transmitted using the fourth pin;
• accessing data associated with the read address in the memory device;
• waiting a predetermined number of clock cycles, the predetermined number of clock cycles being associated with the wait cycle count;
• and
• transferring the data from the memory device using the first pin, the second pin, the third pin, and the fourth pin concurrently.

A method for page read in an integrated circuit which includes a memory device, a clock signal and a plurality of pins, the method comprising:

• transmitting a first page read address to the memory device using a first input pin and a second input pin concurrently, the first page read address being associated with a location in the memory;
• transferring data from the memory device using a first output pin and a second output pin concurrently, the data being associated with the first page read address in the memory device;
• transmitting a second page read address to the memory device using the first input pin and the second input pin concurrently, while continuing to transfer the data associated with the first page read address from the memory device using the first output pin and the second output pin concurrently;
• and
• transferring data associated with the second page read address from the memory device using the first output pin and the second output pin concurrently.

A method for simultaneous read/write operation in an integrated circuit which includes a memory device, a clock signal, a plurality of pins, and a configuration register, the configuration register including a wait cycle count, a burst read length, and a wrap around indicator, the method comprising:

• entering a read command into the memory device using a second input pin;
• transmitting a read address to the memory device using the first input pin and a second input pin concurrently, the read address being associated with a location in the memory device, the read address including at least a first address bit and a second address bit, the first address bit being transmitted using the first input pin, the second address bit being transmitted using the second input pin;
• accessing read data associated with the read address in the memory device;
• transferring the read data in burst mode from the memory device using a first output pin and a second output pin concurrently, a length of the read data being associated with the burst read length;
• and
• performing a write operation in the memory device using the first input pin and second input pin while continuing to transfer the read data in burst mode using the first output pin and the second output pin, the write operation including at least one of the following processes:
• entering a write command into the memory device using the second input pin;
• transferring a write address to the memory device using the first input pin and the second input pin concurrently;
• and
• transferring write data to the memory device using the first input pin and the second input pin concurrently.