US 2008/0165586 A1Published application

Semiconductor device

AssigneeKabushiki Kaisha Toshiba

InventorsKensuke MATSUFUJI, Toshimasa Namekawa

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Abstract

A memory cell includes: an irreversible storage element that writes data by breaking down an insulating film, with a write voltage being applied to its one end; and first and second transistors with one end being connected to the other end of the irreversible storage element. A non-volatile semiconductor storage device includes: the memory cell; write word lines and read word lines that are connected to the first transistor and the second transistor, respectively; write bit lines and read bit lines that are connected to the first transistor and the other end of the second transistor, respectively; a row decoder selectively driving the write word lines and the read word lines; and a write-disturb prevention circuit charging the read bit lines to a certain voltage in writing data.

Claims15

Dependent claims

A non-volatile semiconductor storage device comprising:

a memory cell array including a plurality of memory cells arranged in a grid configuration, each of the plurality of memory cells comprising an irreversible storage element adapted to write data by breaking down an insulating film, with a write voltage being applied to its one end, a first transistor with its one end being connected to the other end of the irreversible storage element, and a second transistor with its one end being connected to the other end of the irreversible storage element;
a plurality of write word lines connected to a gate of the first transistor to select the memory cell in a row direction in writing data;
a plurality of read word lines connected to a gate of the second transistor to select the memory cell in a row direction in reading data;
write bit lines connected to the other end of the first transistor to write data to the memory cells;
read bit lines connected to the other end of the second transistor to read data from the memory cells;
a row decoder selectively driving the write word lines and the read word lines according to an address signal;
and
a write-disturb prevention circuit for, in writing data, charging the read bit lines to a certain voltage.

5 more elements

A non-volatile semiconductor storage device comprising:

a memory cell array including a plurality of memory cells arranged in a grid configuration, each of the plurality of memory cells comprising an irreversible storage element adapted to write data by breaking down an insulating film, with a write voltage being applied to its one end, a first transistor with its one end being connected to the other end of the irreversible storage element, and a second transistor with its one end being connected to the other end of the irreversible storage element;
a plurality of write word lines connected to a gate of the first transistor to select the memory cell in a row direction in writing data;
a plurality of read word lines connected to a gate of the second transistor to select the memory cell in a row direction in reading data;
write bit lines connected to the other end of the first transistor to write data to the memory cells;
read bit lines connected to the other end of the second transistor to read data from the memory cells;
a row decoder selectively driving the write word lines and the read word lines according to an address signal and a test signal;
and
a data input/output block applying a first voltage to the write bit lines and a second voltage to the read bit lines according to an input signal and the test signal, the second voltage being different from the first voltage.

5 more elements

Dependencies are inferred from the claim text.