Back to results
US 2008/0165584 A1Published application
Flash Memory Array Architecture
AssigneeMacronix International Co., Ltd. (A Taiwanese Corporation
InventorsJian-Yuan Shen, Chi-Ling Chu, Chou-Ying Yang
Life of this patent
Estimating the term…
Abstract
A memory device comprises a memory array of memory cells for storing data and an information array of information cells for storing operating information. The information array is coupled to the memory array so that the information array and the memory array share the same data path circuitry for reading, erase or programming operations. A power-on control circuit controls the operation of the information array.
Claims19
A memory device comprising:
- a main array including
- a memory array having a number of memory cells for storing data,
- a number of word lines each coupled to at least one of the memory cells in a corresponding row,
- a number of bit lines each coupled to at least one of the memory cells in a corresponding column, and
- an information array having a number of information cells for storing operating information, wherein each of the information cells is coupled to one of the bit lines;
- a data path circuit coupled to the memory array and the information array, the memory array and the information array being capable of sharing the data path circuit;
- and
- a control circuit coupled to the data path circuit for controlling operation of the memory array and the information array.
5 more elements
A memory device, comprising:
- a main array including
- a memory array having a number of memory cells for storing data,
- a number of word lines each coupled to at least one of the memory cells in a corresponding row,
- a number of bit lines each coupled to at least one of the memory cells in a corresponding column and
- an information array having a number of information cells for storing operating information, wherein each of the information cells is coupled to one of the bit lines;
- a data path circuit coupled to the main array;
- a control circuit coupled to the data path circuit for controlling operation of the memory array and the information array,
- an information register coupled to the data path circuit,
- wherein the information array and the memory array are capable of sharing the data path circuit.
6 more elements
A method of operating a memory device, the method comprising:
- providing a memory array having a number of memory cells for storing data;
- providing an information array having a number of information cells for storing operating information;
- sharing a data path circuit between the memory array and the information array;
- and
- providing a control circuit for controlling the operation of the memory array and the information array.
2 more elements
Dependencies are inferred from the claim text.