US 2008/0165582 A1Published application

Scalable Electrically Eraseable And Programmable Memory

AssigneeCatalyst Semiconductor, Inc.

InventorsSorin S. Georgescu, Peter Cosmin, George Smarandoiu

Life of this patent

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Abstract

A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor, a second non-volatile memory transistor and a source access transistor. The source access transistor includes: a first source region continuous with a source region of the first non-volatile memory transistor; a second source region continuous with a source region of the second non-volatile memory transistor, and a third source region continuous with source regions of other non-volatile memory transistors located in the same row as the EEPROM cell pair.

Claims7

Dependent claims

A non-volatile memory array comprising:

one or more electrically erasable and programmable memory (EEPROM) cell pairs, each configured to store two data bits, and including:
a first non-volatile memory transistor having a floating gate structure separated from a control gate structure by an inter-gate dielectric layer;
a second non-volatile memory transistor having a floating gate structure separated from a control gate structure by an inter-gate dielectric layer;
and
a source access transistor having a floating gate structure electrically connected with a control gate structure, the source access transistor located in a first well region and coupled to a source of the first non-volatile memory transistor and a source of the second non-volatile memory transistor, wherein first well region is located in a second well region.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/050,491Filed 18 Mar 2008
Priority: 5 Sep 2006
Published: 10 Jul 2008
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

G11C 16/0458
Comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates:…
H10B 41/40
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the peripheral circuit region
H10B 41/41
Characterised by the peripheral circuit region: of a memory region comprising a cell select transistor, e.g. NAND
H10D 84/0181
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their gate insulating layers

Family

Application11/470,245Continuation in part · filed 5 Sep 2006
Application12/050,491Continuation in part
US 2008/0054336 A1Published application
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US 2008/0165582 A1This patent

From the US filing history. Foreign family members aren’t listed.