Non-volatile semiconductor memory device having non-selected word lines adjacent to selected word lines being charged at different timing for program disturb control

A non-volatile semiconductor memory device, comprising:

• a memory cell array of memory cell units each including data-rewritable non-volatile memory cells and first and second selection transistors;
• a plurality of word lines each commonly connected to said memory cells on the same row in said memory cell array;
• a first gate line commonly connected to gates of said first selection transistors on the same row in said memory cell array;
• and
• a second gate line commonly connected to gates of said second selection transistors on the same row in said memory cell array,
• wherein in write pulse applying during data writing, a high voltage for writing is applied to a selected word line, a first intermediate voltage for writing is applied to at least one of non-selected word lines, and a second intermediate voltage for writing is applied to at least one of non-selected word lines,
• wherein the beginning of charging a first word line as one of said non-selected word lines located between said selected word line and said first selection gate line from a first voltage to said first intermediate voltage for writing is followed by the beginning of charging a second word line as one of said non-selected word lines located between said selected word line and said second selection gate line from a second voltage to said second intermediate voltage for writing,
• said first voltage being lower than a supply voltage, said second voltage being lower than said supply voltage, and said first and second intermediate voltages being higher than said supply voltage,
• and wherein the second intermediate voltage at a first period when the high-voltage for writing is applied to the selected word line is substantially equal to the first intermediate voltage at a second period before the high voltage for writing is applied to the selected word line.