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US 2008/0165577 A1Published application
Semiconductor device
OwnerPierre Fazan, Serguel Okhonininventors
Life of this patent
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Abstract
A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate and the drain and between the source and the drain.
Claims25
An integrated circuit device comprising:
- a memory array, comprising:
- a plurality of dynamic random access memory cells arranged in a matrix having a plurality of rows and columns, each dynamic random access memory cell comprises a transistor comprising:
- a source region;
- a drain region;
- a body region disposed between the source region and the drain region, wherein the body region is electrically floating;
- and
- a gate spaced apart from the body region;
- and
- wherein each memory cell includes three or more data states including:
- (1) a first data state which corresponds to a first charge in the body region of the transistor of the memory cell, (2) a second data state which corresponds to a second charge in the body region of the transistor of the memory cell, and (3) a third data state which corresponds to a third charge in the body region of the transistor of the memory cell.
7 more elements
An integrated circuit device comprising:
- a memory array, comprising:
- a plurality of memory cells arranged in matrix having a plurality of rows and columns, each memory cell consists essentially of a transistor comprising:
- a source region;
- a drain region;
- a body region disposed between the source region and the drain region, wherein the body region is electrically floating;
- and
- a gate spaced apart from the body region;
- and
- wherein each memory cell includes three or more data states including:
- (1) a first data state which corresponds to a first charge in the body region of the transistor of the memory cell, (2) a second data state which corresponds to a second charge in the body region of the transistor of the memory cell, and (3) a third data state which corresponds to a third charge in the body region of the transistor of the memory cell.
7 more elements
An integrated circuit device comprising
- a semiconductor memory array, disposed in or on a semiconductor region or layer which resides on or above an insulating region or layer of a substrate, the semiconductor memory array comprising:
- a plurality of semiconductor memory cells disposed in or on the semiconductor region or layer, wherein each semiconductor memory cell comprises a transistor comprising:
- a source region having impurities to provide a first conductivity type;
- a drain region having impurities to provide the first conductivity type,
- a body region disposed between the source region, the drain region and the insulating region or layer of the substrate, wherein the body region is electrically floating and includes impurities to provide a second conductivity type wherein the second conductivity type is different from the first conductivity type;
- and
- a gate spaced apart from the body region;
- and
- wherein each memory cell includes three or more data states including:
- (1) a first data state which corresponds to a first charge in the body region of the transistor of the memory cell, (2) a second data state which corresponds to a second charge in the body region of the transistor of the memory cell, and (3) a third data state which corresponds to a third charge in the body region of the transistor of the memory cell wherein at least one of the data states is at least partially provided by removing majority carriers from the body region through the source region of the transistor of the memory cell.
7 more elements
An integrated circuit device comprising
- a semiconductor memory array, disposed in or on a semiconductor region or layer which resides on or above an insulating region or layer of a substrate, the semiconductor memory array comprising:
- a plurality of memory cells, arranged in a plurality of rows and columns and disposed in or on the semiconductor region or layer, wherein each memory cell consists essentially of a transistor comprising:
- a source region having impurities to provide a first conductivity type;
- a drain region having impurities to provide the first conductivity type,
- a body region disposed between the source region, the drain region and the insulating region or layer of the substrate, wherein the body region is electrically floating and includes impurities to provide a second conductivity type wherein the second conductivity type is different from the first conductivity type;
- and
- a gate spaced apart from the body region;
- and
- wherein each memory cell includes three or more data states including:
- (1) a first data state which corresponds to a first charge in the body region of the transistor of the memory cell, (2) a second data state which corresponds to a second charge in the body region of the transistor of the memory cell, and (3) a third data state which corresponds to a third charge in the body region of the transistor of the memory cell.
7 more elements
Dependencies are inferred from the claim text.