Memory cell array biasing method and a semiconductor memory device

A method of writing data to a selected memory cell connected to a selected first line and a selected second line of a semiconductor memory device including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line of a plurality of first lines and a second terminal of the memory cell is connected to a corresponding second line of a plurality of second lines the method comprising:

• biasing the selected first line to a predetermined voltage;
• biasing the selected second line to a first voltage;
• and
• basing non-selected second lines to a second voltage, wherein the first voltage is a decoded word line address voltage and the second voltage is a pumping voltage.

A semiconductor memory device comprising:

• a plurality of first lines and a plurality of second lines;
• and
• a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding one of the first lines and a second terminal of a memory cell is connected to a corresponding one of the second lines;
• wherein a selected second line is biased to a first voltage;
• and
• non-selected second lines are biased to a second voltage, wherein the first voltage is a decoded word line address voltage and the second voltage is a pumping voltage.

A semiconductor memory device comprising:

• a memory cell array including a plurality of phase change memory cells in which a first terminal of a phase change memory cell is connected to a corresponding first line of a plurality of first lines and a second terminal of a phase change memory cell is connected to a corresponding second line of a plurality of second lines;
• and
• inverters for biasing a selected second line to a first voltage and non-selected second lines to a second voltage in response to main word line signals,
• wherein the first voltage is a decoded word line address voltage and the second voltage is a pumping voltage.