Non-volatile semiconductor storage device
AssigneeKabushiki Kaisha Toshiba
InventorToshimasa NAMEKAWA
Life of this patent
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Abstract
A memory cell array includes memory cells disposed in a matrix. A plurality of word-lines are arranged in the memory cell array to select a memory cell in a row direction. A read bit-line pair is arranged in a direction perpendicular to the word-line to read data from the memory cell. In addition, a write bit-line is arranged in a direction perpendicular to the word-line to write data to the memory cell. The read bit-line pair includes a true and a complementary read bit-line. One of the true and complementary read bit-lines is connected to the memory cell connected to an even-numbered word-line. The other one is connected to the memory cell connected to an odd-numbered word-line.
Claims15
A non-volatile semiconductor storage device comprising:
- a memory cell array comprising memory cells disposed in a matrix;
- a plurality of word-lines arranged in the memory cell array, the word-lines being for selecting a memory cell in a row direction;
- a read bit-line pair arranged in a direction perpendicular to the word-line, the read bit-line pair being for reading data from the memory cell;
- a write bit-line arranged in a direction perpendicular to the word-line, the write bit-line being for writing data to the memory cell;
- and
- a sense amplifier amplifying a potential difference generated across the read bit-line pair,
- the read bit-line pair comprising a true and a complementary read bit-line, one of the true and complementary read bit-lines being connected to a memory cell connected to an even-numbered word-line, and the other one being connected to a memory cell connected to an odd-numbered word-line.
Dependencies are inferred from the claim text.