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US 2008/0165562 A1Published application
Fast, stable, sram cell using seven devices and hierarchical bit/sense line
AssigneeInternational Business Machines Corporation
InventorsRichard E. Matick, Stanley E. Schuster
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Abstract
An embodiment of the present invention is an SRAM memory array comprising memory cells with each cell containing seven devices, wherein the basic storage nodes, which store the true and complement of the data, are constructed from six devices, forming a cross-coupled flip-flop cell. One internal storage node of this cell being connected to a separate read-pass device which passes the state of this node to a local bit line (LBL) for single-ended sensing, with the gate of this separate read-pass device connected to a separate read-word line.
Claims6
An SRAM memory array comprising:
- a plurality of memory cells, each of said plurality of memory cells further comprising:
- a device, each of said plurality of memory cells having seven of said device;
- a first storage node;
- a second storage node;
- and
- a first local bit line;
- said first storage node and said second storage node store true and complement of data and are constructed with six of said device forming a cross-coupled flip-flop cell, one of said device being configured as a first read-pass device, said second storage node is connected to said first read-pass device, said first read-pass device passes the state of said second storage node to said first local bit line effectuating single ended sensing, said first read-pass device gate is connected to a first read word line.
4 more elements
Dependencies are inferred from the claim text.