Hierarchical 2T-DRAM with Self-Timed Sensing
AssigneeInternational Business Machines Corporation
InventorsRichard E. Matick, Stanley E. Schuster
Life of this patent
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Abstract
An embodiment of the present invention is an array of 2 transistor DRAM cells organized in rows and columns in which the rows represent words and columns represent bits of the words, each bit column having a pair of balanced, true and complement bit lines, the bit lines being connected in a hierarchical bit line structure, comprising at least one local bit line pair and one global bit line pair, a sensing circuit connected to the global bit line pair detects a differential voltage transition on either line during a read access and provides a sensing strobe signal.
Claims6
A DRAM memory array comprising:
- a plurality of memory cells, each of said plurality of memory cells further comprising:
- a device, each of said plurality of memory cells having two of said device organized in a row representing a plurality of words and a bit column representing bits of said plurality of words, each said bit column having a true bit line, and a complement bit line, said true bit line and said complement bit line being balanced and connected in a hierarchical bit line structure, said hierarchical bit line structure comprising a local bit line true, a local bit line complement, a global bit line true, a global bit line complement, and a sensing circuit, said sensing circuit connected to said global bit line true and said global bit line complement effectuating detecting of a differential voltage transition on either line during a read access and providing a sensing strobe signal.
Dependencies are inferred from the claim text.