Data line layout and line driving method in semiconductor memory device

A data line layout structure in a semiconductor memory device, comprising:

• a plurality of first data lines connected to sub mats in a memory mat, a predetermined number of first data lines being connected to each sub mat;
• second data lines being fewer in number than the first data lines and being disposed so as to form a hierarchy with respect to the first data lines;
• a third data line disposed to be higher in the hierarchy with respect to the second data lines, the third data line transferring data provided through the second data lines to a data latch;
• a first data line driver connected between the first data lines and the second data lines, the first data line driver performing a logical ORing operation on output of the first data lines so as to drive a corresponding second data line;
• and
• a second data line driver connected between the second data lines and the third data line, the second data line driver performing a logical ORing operation on output of the second data lines so as to drive the third data line.

A method of driving a line in a semiconductor memory device, the method comprising:

• disposing data lines in a hierarchical structure of a local main data line, a sub global main data line and a global main data line so as to form a hierarchical structure of the data lines to form a data path between input/output sense amplifiers and a data latch;
• performing a first logical ORing operation of discharging a corresponding sub global main data line of the hierarchical structure from a precharge level to a ground level when one of the local main data lines has a first state level;
• and
• performing a second logical ORing operation of discharging a corresponding global main data line of the hierarchical structure from a precharge level to a ground level when one of the sub global main data lines has a first state level.