Semiconductor memory device

A semiconductor memory device, comprising:

• memory cells each of which has a MIS type of transistor capable of setting one of two kinds of threshold potentials;
• reference cells used for determining data stored in the memory cells, which have the same size, shape and electrical properties as those of the memory cells;
• word lines connected to gates of the memory cells;
• reference word lines connected to gates of the reference cells;
• source line contacts connected to sources of the memory cells and the reference cells;
• and
• bit line contacts connected to drains of the memory cells and the reference cells,
• arrangement order of the source line contact, the word line and bit line contact connected to each of the memory cells is equal to arrangement order of the source line contact, the reference word line and the bit line contact connected to the reference cell corresponding to the memory cell,
• and further comprising:
• one pair of sense amplifiers which sense and amplify data read out from the memory cells;
• and
• bit line pairs each of which is provided corresponding to each of the sense amplifiers, connected alternatively to each sense amplifier, and arranged between the one pair of sense amplifiers,
• wherein two bit lines in the bit line pair are crossed to each other not to be short-circuited between the one pair of sense amplifiers.