Three-dimensional architecture for self-checking and self-repairing integrated circuits

A three-dimensional architecture chip, comprising:

• a stack of integrated circuit (IC) chips, each IC chip being individually manufactured and assembled into the stack by aligning the IC chips and bonding the chips together;
• the stack including:
• a first IC chip including an integrated unit configured to perform electrical signal operations;
• a second IC chip including a component to service the integrated unit, wherein the first integrated circuit chip and the second integrated circuit chip are configured to permit vertical proximity between the integrated unit and the component, when aligned for bonding;
• and
• at least one electrical connection connecting the integrated unit to the component through vertical layers of at least one of the first IC chip and the second IC chip.

A method for fabricating a three-dimensional architecture chip, comprising:

• constructing a first chip with an integrated unit located at a first position, the integrated unit configured to perform electrical signal operations;
• separately constructing an active layer, the active layer including a component to service the unit of the base chip, the component being locating on the active layer at a second position;
• aligning the active layer to the first chip such that the integrated unit is vertically proximate to the component;
• bonding the active layer to the base chip such that the component is aligned in vertical proximity of the unit;
• and
• forming at least one electrical connection connecting the unit to the component through vertical layers of at least one of the first chip and the active layer.