US 2008/0165459 A1 · Pad ESD Spreading Technique

Abstract

A system, e.g. an integrated circuit or part, may include a plurality of pads, e.g. digital I/O pads, each comprising a physical pad and associated pad circuit. In case of an ESD event affecting one or more of the digital I/O pads, PMOS devices configured in an output buffer section between an I/O pad supply rail and the physical output pad—within their respective pad circuits in the affected digital I/O pads—may all be turned on in response to the ESD event. This may allow the capacitance of each pad, in some cases approximately 3 pF capacitance per pad, to charge up, absorbing the energy of the ESD event and reducing the peak voltage the integrated circuit or part experiences as a result of the ESD event. The reduced peak voltage may be directly correlated with improved ESD performance of the product.

Claims27

Dependent claims

A pad circuit configured to provide protection against electrostatic discharge (ESD) in a system comprising the pad circuit, the pad circuit comprising:

a first node coupled to a first voltage rail;
a second node coupled to a physical pad having capacitance;
one or more output transistor devices coupled between the first node and the second node, and operable to at least partially drive an output signal at the second node;
and
a control block operable to turn on at least one of the one or more output transistor devices in response to an ESD event to charge the pad capacitance, thereby reducing a maximum voltage developed in the system as a result of the ESD event.

2 more elements

Dependencies are inferred from the claim text.

Pad ESD Spreading Technique

Life of this patent

Pad ESD Spreading Technique

Life of this patent

Abstract

Claims27