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US 2008/0165178 A1Published application
Methods for adjusting the synchronization in digital display application
AssigneeTerawins, Inc.
InventorsCyrus Chu, Wen-Yi Huang
Life of this patent
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Abstract
The present invention is to provide two methods for trimming output HSync in display timing conversion for digital display application, so that the scaling controller can minimize Line Buffer timing shift and match the VSync/HSync timing requirement of digital display device. “Horizontal synchronization vibration” and “Remapping” are the two methods of the present invention.
Claims3
A method for adjusting the synchronization in digital display application, in a digital display, the vertical timing is partitioned into four segments:
- VSync_PulseTime (Vertical Synchronization Pulse Time), VSync_BackPorch (Vertical Synchronization Back Porch), V_Display_Active (Vertical Display Active), and VSync_FrontPorch (Vertical Synchronization Front Porch);
- wherein a preset output clock and a Horizontal Sync Output Total Dots is used to calculate a Vertical output Total lines, an integer part of the calculation is used as the Vertical output Total lines, while a fraction part of the calculation can be recalculated into a Dots of last fraction line by the Horizontal Sync Output Total Dots, then remap the Dots of last fraction line to previous output line buffers.
Dependencies are inferred from the claim text.