Systems for displaying images by utilizing vertical shift register circuit to generate non-overlapped output signals

A system for displaying images, comprising:

• a dynamic shift register, comprising:
• a sampling unit, coupled to an incoming signal and a first input terminal of the dynamic shift register, and operative to sample the incoming signal according to a first input signal received by the first input terminal to generate a sampled value, the sampling unit comprising at least a MOSFET having a gate controlled by the first input signal;
• a holding unit, coupled to the sampling unit, and operative to hold the sampled value, the holding unit comprising a capacitor having a first terminal coupled to a voltage level and a second terminal coupled to the sampling unit;
• and
• a first logic circuit, coupled to a second input terminal of the dynamic shift register, the holding unit and an output terminal of the dynamic shift register, and operative to allow a second input signal inputted into the second input terminal to adjust an output signal outputted at the output terminal when the sampled value held by the holding unit has a specific logic level.

A system for displaying images, comprising:

• a vertical shift register circuit operative to generate non-overlapped signals, comprising:
• a plurality of dynamic shift registers connected in a series, each dynamic shift register comprising:
• a sampling unit, coupled to an incoming signal and a first input terminal of the dynamic shift register, and operative to sample the incoming signal according to a first input signal received by the first input terminal to generate a sampled value;
• a holding unit, coupled to the sampling unit, and operative to hold the sampled value, wherein the sampled value is outputted as a first output signal at the a first output terminal;
• and
• a first logic circuit, coupled to a second input terminal of the dynamic shift register, the holding unit, and a second output terminal of the dynamic shift register, and operative to generate a second output signal according to the held sampled value and a second input signal inputted into the second input terminal;
• wherein each dynamic shift register, except an initial dynamic shift register, receives the first output signal of a preceding dynamic shift register as the present incoming signal, and two adjacent dynamic shift registers receive two clock signals alternatively as the first input signal and the second input signal.