Data throttling circuit and method for a spacewire application

A Data Throttling circuit for a SpaceWire application comprising:

• a first bit generation logic circuit having an output for providing data and an input for receiving a throttle control signal;
• a second bit generation logic circuit having an output for providing data and an input for receiving the throttle control signal;
• a first flip-flop having an input coupled to the output of the first bit generation logic circuit, a clock input for receiving a clock signal, and an output for providing output data;
• a second flip-flop having an input coupled to the output of the second bit generation logic circuit, a clock input for receiving the clock signal, and an output for providing output data;
• a first multiplexer having a first input coupled to the output of the first flip-flop, a second input coupled to the output of the second flip-flop, a control node for receiving a first control signal, and an output for providing output data;
• and
• a second multiplexer having a first input coupled to the output of the first flip-flop, a second input coupled to the output of the second flip-flop, a control node for receiving a second control signal, and an output for providing output data,
• wherein, in an open throttle condition output data is able to change on every clock cycle, and, in a closed throttle condition current output data is held until the closed throttle condition is released.

A Data Throttling circuit for a SpaceWire application comprising:

• a first bit generation logic circuit having an output for providing data and an input for receiving a throttle control signal;
• a second bit generation logic circuit having an output for providing data and an input for receiving the throttle control signal;
• a third bit generation logic circuit having an output for providing data and an input for receiving the throttle control signal;
• a fourth bit generation logic circuit having an output for providing data and an input for receiving the throttle control signal;
• a first flip-flop having an input coupled to the output of the first bit generation logic circuit, a clock input for receiving a clock signal, and an output for providing output data;
• a second flip-flop having an input coupled to the output of the second bit generation logic circuit, a clock input for receiving the clock signal, and an output for providing output data;
• a third flip-flop having an input coupled to the output of the third bit generation logic circuit, a clock input for receiving the clock signal, and an output for providing output data;
• a fourth flip-flop having an input coupled to the output of the second bit generation logic circuit, a clock input for receiving the clock signal, and an output for providing output data;
• a first multiplexer having a first input coupled to the output of the first flip-flop, a second input coupled to the output of the second flip-flop, a third input coupled to the output of the third flip-flop, a fourth input coupled to the output of the fourth flip-flop, a control node for receiving a first control signal, and an output for providing output data;
• and
• a second multiplexer having a first input coupled to the output of the first flip-flop, a second input coupled to the output of the second flip-flop, a third input coupled to the output of the third flip-flop, a fourth input coupled to the output of the fourth flip-flop, a control node for receiving a second control signal, and an output for providing output data,
• a third multiplexer having a first input coupled to the output of the first flip-flop, a second input coupled to the output of the second flip-flop, a third input coupled to the output of the third flip-flop, a fourth input coupled to the output of the fourth flip-flop, a control node for receiving a third control signal, and an output for providing output data;
• and
• a fourth multiplexer having a first input coupled to the output of the first flip-flop, a second input coupled to the output of the second flip-flop, a third input coupled to the output of the third flip-flop, a fourth input coupled to the output of the fourth flip-flop, a control node for receiving a fourth control signal, and an output for providing output data,
• wherein, in an open throttle condition output data is able to change on every clock cycle, and, in a closed throttle condition current output data is held until the closed throttle condition is released.

A Data Throttling method for a SpaceWire application comprising:

• providing output data;
• and
• providing a clock signal,
• wherein, in an open throttle condition output data is able to change on every clock cycle of the clock signal, and, in a closed throttle condition current output data is held until the closed throttle condition is released.

A Data Throttling method for a SpaceWire application comprising:

• providing an output data pair;
• and
• providing a clock signal,
• wherein, in an open throttle condition output data is able to change on every clock cycle of the clock signal, and, in a closed throttle condition current output data is held until the closed throttle condition is released.

A Data Throttling method for a SpaceWire application comprising:

• providing a four-bit output data word;
• and
• providing a clock signal,
• wherein, in an open throttle condition output data is able to change on every clock cycle of the clock signal, and, in a closed throttle condition current output data is held until the closed throttle condition is released.