Data output strobe signal generating circuit and semiconductor memory apparatus having the same
AssigneeHynix Semiconductor Inc.
InventorsWon-Joo Yun, Hyun-Woo Lee
Life of this patent
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Abstract
A data output strobe signal generating circuit includes a duty cycle correcting unit that corrects the duty ratio of an input clock in response to a control signal to generate a corrected clock. A data output strobe signal generating unit receives the corrected clock and generates a data output strobe signal. A duty cycle control unit receives the data output strobe signal and outputs the control signal.
Claims33
A data output strobe signal generating circuit comprising:
- a duty cycle correcting unit configured to correct a duty cycle of an input clock in response to a control signal, thereby outputting a corrected clock;
- a data output strobe signal generating unit configured to receive the corrected clock, thereby generating a data output strobe signal;
- and
- a duty cycle control unit configured to receive the data output strobe signal, thereby outputting the control signal.
A semiconductor memory apparatus comprising:
- a DLL circuit configured to generate a DLL clock having a phase which leads a phase of an external clock by a predetermined amount of time;
- a transmission line configured to transmit the DLL clock;
- a data output strobe signal generating circuit configured to correct a duty cycle of the DLL clock transmitted through the transmission line to obtain a corrected clock, thereby generating a data output strobe signal using the corrected clock;
- and
- a data output buffer configured to receive the data output strobe signal, thereby buffering output data.
A method of generating a data output strobe signal, comprising:
- correcting a duty ratio of an input clock in response to a control signal to generate a corrected clock;
- generating a data output strobe signal from the corrected clock;
- and
- receiving the data output strobe signal, thereby outputting the control signal.
A method of controlling a semiconductor memory apparatus, comprising:
- generating a DLL clock having a phase which leads a phase of an external clock by a predetermined amount of time;
- correcting a duty cycle of the DLL clock to obtain a corrected clock and generating a data output strobe signal using the corrected clock;
- and
- receiving the data output strobe signal and buffering output data.
Dependencies are inferred from the claim text.