DLL circuit and method of controlling the same
AssigneeHynix Semiconductor Inc.
InventorKwang Jun Cho
Life of this patent
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Abstract
A DLL circuit includes a duty ratio correction unit that corrects the duty ratios of first and second delay clocks duty ratio to generate first and second correction clocks. A duty ratio detection unit detects the duty ratios of the first and second correction clocks, thereby generating first and second detection signals. A voltage comparison unit compares the levels of the first and second detection signals, thereby generating a first fine control signal. An operation mode setting unit generates a locking completion signal and a second fine control signal. A switching unit selectively transmits the first fine control signal or the second fine control signal to a delay control unit according to whether or not the locking completion signal is enabled.
Claims38
A DLL (Delay Locked Loop) circuit comprising:
- a duty ratio correction unit configured to correct duty ratios of first and second delay clocks to generate first and second correction clocks;
- a duty ratio detection unit configured to detect duty ratios of the first and second correction clocks, thereby generating first and second detection signals;
- a voltage comparison unit configured to compare levels of the first and second detection signals, thereby generating a first fine control signal;
- an operation mode setting unit configured to generate a locking completion signal and a second fine control signal;
- and
- a switching unit configured to selectively transmit the first fine control signal or the second fine control signal to a delay control unit according to whether or not the locking completion signal is enabled;
A DLL circuit comprising:
- a first feedback loop configured to receive a reference clock from a clock input buffer and to output a first clock;
- and
- a second feedback loop configured to receive the reference clock, when a delay locking operation is in progress, to generate a second clock by linking with an operation to generate the first clock, and, if the delay locking operation is completed, to correct duty ratios of the first and second clocks.
A method of controlling a DLL circuit, the method comprising:
- receiving a reference clock from a clock input buffer and performing a delay locking operation using first and second feedback loops to output first and second clocks;
- and
- correcting duty ratios of the first and second clocks using the second feedback loop while generating the first clock by applying a fixed delay time to the reference clock using the first feedback loop.
Dependencies are inferred from the claim text.